The present invention relates generally to manufacturing and testing of semiconductor devices, more particularly, to determining die test protocols based on process health.
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost of integrated circuit devices incorporating such transistors.
Generally, a distinct sequence of processing steps is performed on a lot of wafers using a variety of processing tools, including photolithography steppers, etch tools, deposition tools, polishing tools, rapid thermal processing tools, implantation tools, etc., to produce final products that meet certain electrical performance requirements. In some cases, electrical measurements that determine the performance of the fabricated devices are not conducted until relatively late in the fabrication process, and sometimes not until the final test stage.
During the fabrication process various events may take place that affect the end performance of the devices being fabricated. That is, variations in the fabrication process steps result in device performance variations. Factors, such as feature critical dimensions, doping levels, contact resistance, particle contamination, etc., all may potentially affect the end performance of the device. Devices are typically ranked by a grade measurement, which effectively determines its market value. In general, the higher a device is graded, the more valuable the device.
The electrical tests performed after the fabrication of the device determine its final grade and functionality. A wide variety of tests may be performed. Exemplary tests include: final wafer electrical tests (FWET) that evaluate discrete test structures like transistors, capacitors, resistors, interconnects and relatively small and simple circuits, such as ring oscillators at various sites on a wafer; sort tests that sort die into bins (categories of good or bad) after testing functionality of each die; burn-in tests that test packaged die under temperature and/or voltage stress; automatic test equipment (ATE) tests that test die functionality using a test protocol that is a superset of sort; and system-level tests (SLT) that test packaged die in an actual motherboard by running system-level tests (e.g., booting the operating system).
The variety of electrical tests that devices must undergo consume considerable metrology resources, and may present a production bottleneck. Due to the complexity of integrated circuit devices, and the costs associated with screening devices to identify which are most at-risk, it is often difficult to identify the populations at risk for which increased metrology should be provided. Typically, fixed metrology sampling plans are employed for electrical testing. Such fixed sampling plans may, in some cases, result in reduced efficiency by implementing excessive testing, while in other cases, may result in the failure to adequately identify faulty devices.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the present invention described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the present invention. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.